This invention relates to a composite semiconductor device having a junction field effect transistor merged with a bipolar transistor and exhibiting high input impedance and high transconductance.
Junction field effect transistors, or JFETS, as they are commonly known, are devices whose output current is controlled by an input voltage. Their characteristically high input impedance, therefore, makes them useful in many analog applications because they do not load signal sources connected to their inputs. One of their major shortcomings, however, is their relatively low transconductance as compared with that of a bipolar transistor.
It has been known to combine a JFET with a bipolar transistor to multiply the effective transconductance, but in the past such bipolar-field effect transistor combination has not found widespread use because of the heretofore incompatible processing requirements of the two devices. Recent developments in analog circuitry fabrication, such as the application of ion implantation, has permitted bipolar and FET fabrication in the same analog circuitry.
This invention carries the above developments one step further by merging a junction field effect transistor with a bipolar transistor in a single composite device within a single isolation region by the use of planar processing techniques.